Via auto retarget application in 28nm technology node

In 28nm technology node, developing an enough lithographic process window of VIA layer became a major challenge in order to meet the requirements of the connectivity between metal lines. It is widely used to size up VIA in order to enlarge VIA process window if the space between VIA holes and VIA enclosed by metal is big enough. But the traditional retarget method has its own limits as the retarget rule table cannot deal with every complex environment for each VIA hole. In this paper, we studied several issues in the application of CALIBRE auto-retarget function in VIA model-based OPC correction after the traditional retarget treatment. The parameters of the auto-retarget function are optimized based on simulated results and the SEM data of the corresponding VIA holes are collected for DOF verification. The impact of the auto-retarget function on model-based OPC runtime is also evaluated. It is shown in the simulation result that the DOF of certain SRAM patterns can be enlarged as much as to 30nm after applying the auto-retarget function. The silicon data confirms the simulation prediction and that the DOF of the patterns become enough for lithographic process. Meanwhile, auto-retarget has little impact on model-based OPC runtime.