Title :
A low-power reduced swing single clock flip-flop
Author :
Kim, Chulwoo ; Kang, Sung-Mo
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
Abstract :
A reduced swing single clock flip-flop (RS2CFF) is developed to reduce power consumption significantly compared to conventional FFs. RS2CFF avoids unnecessary internal node transition and reduce fighting currents. The overall power saving in flip-flop operation is estimated to be 33% with additional 64% power savings in clock network
Keywords :
flip-flops; low-power electronics; fighting current; internal node transition; low-power reduced swing single clock flip-flop; power consumption; Capacitance; Clocks; Energy consumption; Flip-flops; MOSFETs; Pipelines; Power dissipation; Power engineering and energy; Power engineering computing; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922360
