Title :
Energy-efficient skewed static logic design with dual Vt
Author :
Kim, Chulwoo ; Kim, Kiwook ; Kang, Sung-Mo
Author_Institution :
Dept. of Electr. Eng., Illinois Univ., Urbana, IL, USA
Abstract :
In this paper, we describe skewed static logic (S2L) with topology-dependent dual Vt which exhibits energy-efficient operation. S2L consumes less dynamic and static power compared to Monotonic Static (MS) CMOS. Speed degradation of S2 L can be offset by the accelerator. We have designed NAND-NOR gate chains using 0.18 μm CMOS technology and verified that S2L reduces energy×delay over MS CMOS by 27-50%. Synthesis algorithm for S2L developed and the experimental results show S2 L consumes 23% less power than MS CMOS with minor increase in delay
Keywords :
CMOS logic circuits; VLSI; delays; integrated circuit design; leakage currents; logic gates; low-power electronics; 0.18 micron; CMOS technology; NAND-NOR gate chains; delay; dynamic power; energy-efficient skewed static logic design; speed degradation; static power; synthesis algorithm; topology-dependent dual voltage; CMOS logic circuits; CMOS technology; Circuit noise; Clocks; Design engineering; Energy consumption; Energy efficiency; Logic design; Logic gates; Power engineering and energy;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922379
