Mapping nested loops to field programmable gate array based systems

The Configurable Hardware Algorithm Mappable Preprocessor (CHAMP) architecture is based on Xilinx 4000 series field programmable gate array (FPGA) devices. These devices make CHAMP a programmable hardware resource that can be used to process data in real time. Recently the task of mapping Reed-Solomon decoding onto the CHAMP architecture was undertaken. During the process of mapping a sequential `C´ code to CHAMP, problems related to implementing a highly data dependant algorithm on an FPGA based system were uncovered. One problem that was dealt with, and is examined in this paper is the mapping of nested loops to FPGAs. This paper also provides future directions for improving user interaction with the CHAMP system