Title :
A Bayesian neural network chip design for speech recognition system
Author :
Wang, Jhing-Fa ; Suen, An-Nan ; Lee, Jia-Ru ; Wu, Chung-Hsien
Author_Institution :
Inst. of Inf. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Abstract :
The Bayesian neural network (BNN) has been widely used as speech recognition template which combines the merits of the dynamic programming (DP) and hidden Markov model (HMM) methods. However, it is computationally intensive and very costly to implement using DSP component. A single chip implementation of the BNN will drastically reduce the cost and the size of many speech recognition systems. It will also make low cost implementation of real-time speech recognition system possible. In this paper, the implementation of single BNN chip for the real-time speech recognizer is presented. Fabricated in 0.8 μm double-metal CMOS technology, the chip contains approximately 13000 transistors which occupy a 3.1×3.2 mm2 area and has been tested to be fully functional at IMS XL-60 tester
Keywords :
Bayes methods; CMOS digital integrated circuits; VLSI; hidden Markov models; neural chips; neural net architecture; probability; real-time systems; speech recognition; 0.8 micron; Bayesian neural network; IMS XL-60 tester; VLSI; double-metal CMOS technology; dynamic programming; hidden Markov model; neural chip; probability; real-time systems; speech recognition; Bayesian methods; CMOS technology; Chip scale packaging; Costs; Digital signal processing chips; Dynamic programming; Hidden Markov models; Neural networks; Speech recognition; Testing;
Conference_Titel :
Neural Networks, 1995. Proceedings., IEEE International Conference on
Print_ISBN :
0-7803-2768-3
DOI :
10.1109/ICNN.1995.488985
