DocumentCode
3598967
Title
Hardware architectures for lattice decoders
Author
Burr, A.G. ; Sheppard, J.A.
Author_Institution
York Univ., UK
fYear
1993
fDate
3/22/1993 12:00:00 AM
Firstpage
42583
Lastpage
42588
Abstract
Describes the implementation of decoders for a combined coding and modulation scheme, lattice coding, using a direct hardware structure. The trellis representation of lattice codes is described, and a hardware decoder structure is developed which maps directly to the trellis. An implementation of this structure for the E8 lattice is described, using field programmable gate arrays (FPGAs). This achieves a coding gain of about 2 dB, and is capable of operation at over 60 Mbit/s. The integration of various software tools, including Workview and SPW, in the design process is also described
Keywords
decoding; encoding; logic CAD; logic arrays; modulation; 60 Mbit/s; E8 lattice; FPGA; SPW; Workview; coding gain; field programmable gate arrays; hardware architecture; lattice codes; lattice coding; lattice decoders; modulation; radio LAN; software tools; trellis representation;
fLanguage
English
Publisher
iet
Conference_Titel
DSP Applications in Communication Systems, IEE Colloquium on
Type
conf
Filename
230936
Link To Document