Modeling and Layout Optimization for Tapered TSVs

Through-silicon-via (TSV) offers vertical connections for 3-D ICs. Due to its large dimensions and nonideal etching process, TSVs layout needs to be carefully optimized to balance peak current density and delay for digital circuit. This brief investigates the TSVs tapering effect (which is an inevitable byproduct of deep reactive Ion etching-based manufacturing) and its impact on the TSVs electrical properties. We show that the current crowding effect is more severe in realistic tapered TSVs than ideal cylindrical TSVs. We propose a nonuniform current density model for tapered TSVs, which achieves considerable accuracy and speedup in estimating the current density distribution, when compared with the existing models developed for cylindrical TSVs. We apply our model to perform a detailed study on: 1) impact of TSVs tapering on peak current density and 2) wire sizing problem to minimize TSV-involved path delay under second-order delay model while keeping the peak current density within tolerable levels. A new dynamic programming-based heuristic is proposed to find the optimal wire configuration, which reduces both peak current density and delay, thereby improving the reliability and performance.