DocumentCode :
3601675
Title :
High-Throughput Trellis Processor for Multistandard FEC Decoding
Author :
Zhenzhi Wu ; Dake Liu
Author_Institution :
Beijing Inst. of Technol., Beijing, China
Volume :
23
Issue :
12
fYear :
2015
Firstpage :
2757
Lastpage :
2767
Abstract :
Trellis codes, including Low-Density Parity-Check (LDPC), turbo, and convolutional code (CC), are widely adopted in advanced wireless standards to offer high-throughput forward error correction (FEC). Designing a multistandard FEC decoder is of great challenge. In this paper, a trellis application specified instruction-set processor (TASIP) is presented for multistandard trellis decoding. A unified forward-backward recursion kernel with an eight-state parallel trellis structure is proposed. Based on the kernel, a datapath for multialgorithm and a shared memory subsystem are introduced. The flexibility and the compatibility are guaranteed by a programmable decoding flow and the trellis decoding instruction set. Synthesis results show that the area consumption is 2.12 mm2 (65 nm). TASIP provides trimode FEC decoding ability with the throughput of 533, 186, and 225 Mb/s for LDPC, turbo, and 64 states CC under the clock frequency of 200 MHz, which outperforms other trimode proposals both in area efficiency and recursion efficiency. TASIP provides high-throughput decoding for current standards, including 3rd Generation Partnership Project-Long Term Evolution, 802.16e, and 802.11n, with unified architecture and high compatibility.
Keywords :
forward error correction; instruction sets; shared memory systems; telecommunication computing; trellis codes; CC; LDPC; TASIP; Trellis application specified instruction-set processor; Turbo code; advanced wireless standards; area efficiency; eight-state parallel trellis structure; frequency 200 MHz; high-throughput forward error correction; high-throughput trellis processor; multialgorithm; multistandard FEC decoding; programmable decoding flow; recursion efficiency; shared memory subsystem; trellis codes; trellis decoding instruction set; unified forward-backward recursion kernel; Computer architecture; Decoding; Forward error correction; Iterative decoding; Measurement; Standards; Application-specific instruction-set processor (ASIP); forward--backward recursion (FBR); forward???backward recursion (FBR); multistandard forward error correction (FEC); single instruction multiple data (SIMD); trellis decoding; trellis decoding.;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2014.2382108
Filename :
7066973
Link To Document :
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