Title :
A 0.022 mm
98.5 dB SNDR Hybrid Audio
Modulator With Digital ELD Compe
Author :
Tze-Chien Wang ; Yu-Hsin Lin ; Chun-Cheng Liu
Author_Institution :
MediaTek Inc., Hsinchu, Taiwan
Abstract :
This work presents a compact-area hybrid continuous-time delta-sigma modulator (CTDSM) with a shared 6 bit asynchronous successive approximation register (ASAR) quantizer for audio application. It is implemented in a 28 nm CMOS process. The modulator incorporates an analog integrator and a digital filter. Signal is digitized after the analog first stage and processed digitally thereafter. Only the first stage is left in the analog domain. Because of high integration of digital circuitry, it could benefit from process advancement such as low power consumption and small area. Moreover, the excess loop delay (ELD) is compensated in the digital domain, and the conventional analog local feedback DAC for ELD compensation is no longer needed. In addition, resistive DAC (R-DAC) is adopted for low flicker noise. The measured DR and SNDR in 24 kHz BW are 100.6 dB and 98.5 dB, respectively, while occupying 0.022 mm2 and achieving FOMs (SNDR + 10 *log(BW/Power)) of 171.8 dB.
Keywords :
CMOS integrated circuits; delta-sigma modulation; digital filters; flicker noise; CMOS process; analog integrator; analog local feedback DAC; asynchronous successive approximation register quantizer; compact-area hybrid continuous-time delta-sigma modulator; digital ELD compensation; digital circuitry; digital filter; excess loop delay; frequency 24 kHz; hybrid audio delta-sigma modulator; low flicker noise; size 28 nm; Capacitors; Delays; Modulation; Noise; Power demand; System-on-chip; Transfer functions; Continuous-time delta sigma modulator (CTDSM); asynchronous successive approximation register (ASAR); digital filter; dynamic element matching (DEM); hybrid modulator; oversampling;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2015.2453953