A Double-Sensing-Margin Offset-Canceling Dual-Stage Sensing Circuit for Resistive Nonvolatile Memory

Resistive nonvolatile memory (NVM) devices such as spin transfer torque random access memory (STT-RAM) and resistive random access memory are considered to be leading candidates for next-generation memory devices. With technology scaling, the sensing margin (SM) of the resistive NVM devices is significantly degraded because of increased process variation and decreased read current. In this brief, we propose an offset-canceling dual-stage sensing circuit (OCDS-SC) that has the two major advantages of offset voltage cancelation and double SM. Monte Carlo HSPICE simulation results using a 45-nm technology for STT-RAM show that the OCDS-SC achieves a read access yield of 99.93% for 32 Mb (6.6 sigma) with a read current of 15 μA and sensing time of 3.4 ns.