• DocumentCode
    3605056
  • Title

    A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS

  • Author

    Xiaobao Yu ; Meng Wei ; Yun Yin ; Ying Song ; Siyang Han ; Qiongbing Liu ; Zongming Jin ; Xiliang Liu ; Zhihua Wang ; Yichuang Sun ; Baoyong Chi

  • Author_Institution
    Tsinghua Univ., Beijing, China
  • Volume
    50
  • Issue
    11
  • fYear
    2015
  • Firstpage
    2572
  • Lastpage
    2590
  • Abstract
    A fully-integrated reconfigurable dual-band (760-960 MHz and 2.4-2.5 GHz) transceiver (TRX) for short range wireless communications is presented. The TRX consists of two individually-optimized RF front-ends for each band and one shared power-scalable analog baseband. The sub-GHz receiver has achieved the maximum 75 dBc 3rd-order harmonic rejection ratio (HRR3) by inserting a Q-enhanced notch filtering RF amplifier (RFA). In 2.4 GHz band, a single-ended-to-differential RFA with gain/phase imbalance compensation is proposed in the receiver. A ΣΔ fractional-N PLL frequency synthesizer with two switchable Class-C VCOs is employed to provide the LOs. Moreover, the integrated multi-mode PAs achieve the output P1dB (OP1dB) of 16.3 dBm and 14.1 dBm with both 25% PAE for sub-GHz and 2.4 GHz bands, respectively. A power-control loop is proposed to detect the input signal PAPR in real-time and flexibly reconfigure the PA´s operation modes to enhance the back-off efficiency. With this proposed technique, the PAE of the sub-GHz PA is improved by ×3.24 and ×1.41 at 9 dB and 3 dB back-off powers, respectively, and the PAE of the 2.4 GHz PA is improved by ×2.17 at 6 dB back-off power. The presented transceiver has achieved comparable or even better performance in terms of noise figure, HRR, OP1dB and power efficiency compared with the state-of-the-art.
  • Keywords
    CMOS integrated circuits; notch filters; phase locked loops; radio transceivers; radiocommunication; radiofrequency amplifiers; sigma-delta modulation; voltage-controlled oscillators; ΣΔ fractional-N PLL frequency synthesizer; 3rd-order harmonic rejection ratio; CMOS; Class-C VCO; HRR; PAE; Q-enhanced notch filtering RF amplifier; RF front-ends; frequency 2.4 GHz to 2.5 GHz; frequency 760 MHz to 960 MHz; gain/phase imbalance compensation; power efficiency; power-control loop; power-scalable analog baseband; reconfigurable dual-band transceiver; single-ended-to-differential; size 180 nm; wireless communications; Dual band; Harmonic analysis; Impedance matching; Mixers; Noise; Receivers; Transceivers; CMOS; HRR; PAPR; RF; back-off efficiency enhancement; power amplifier; reconfigurable; wireless transceiver;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.2015.2462345
  • Filename
    7226882