High-order incremental sigma–delta for compressive sensing and its application to image sensors

ΣΔ ADCs show promising perspectives in the field of compressive sensing (CS). A major limitation related to the first-order ΣΔ is its high oversampling ratio (OSR) that is required for a specific bit resolution. An extension to the high-order incremental ΣΔ for the implementation of a dedicated image sensor is presented. By extending the concept of the ΣΔ CS ADC, optimal working points can be reached between the OSR and the compression ratio. Simulations of a particular fourth-order ADC combined with the authors column-based Bernoulli CS scheme show a severe relaxation on the ADC master clock.