Ultralow Turn-OFF Loss SOI LIGBT With p-Buried Layer During Inductive Load Switching

Author

Yitao He ; Ming Qiao ; Xin Zhou ; Zhaoji Li ; Bo Zhang

Author_Institution

State Key Lab. of Electron. Thin Films & Integrated Devices, Univ. of Electron. Sci. & Technol. of China, Chengdu, China

Volume

62

Issue

11

fYear

2015

Firstpage

3774

Lastpage

3780

Abstract

An ultralow turn-OFF loss (EOFF) silicon-oninsulator lateral insulated-gate bipolar transistor with a p-buried layer (PB SOT LTGBT) is first proposed. A universal EOFF model during inductive load turn-OFF is set up, which reveals that low EOFF can be achieved by reducing the total integral current charges, reducing the average anode voltage in the first phase and increasing the charge factor k. Due to the large capacitance effect and extra hole extraction path induced by the PB, the three ideas for low EOFF are demonstrated in the PB SOT LTGBT. Simulation results show that the PB SOT LTGBT can achieve an 85% lower EOFF compared with the conventional SOT LTGBT based on 6-μm SOT layer. Furthermore, the proposed EOFF model can be applied to all the TGBTs, and it reveals the mechanism of low EOFF of the TGBT with a superjunction structure during inductive load switching.

Keywords

buried layers; insulated gate bipolar transistors; silicon-on-insulator; PB SOI LIGBT; anode voltage; capacitance effect; charge factor; hole extraction path; inductive load switching; integral current charge; lateral insulated-gate bipolar transistor; p-buried layer; silicon-on-insulator; superjunction structure; ultralow turn-off loss; Analytical models; Anodes; Capacitance; Insulated gate bipolar transistors; Load modeling; Silicon-on-insulator; Switches; Lateral insulated-gate bipolar transistor (LIGBT); model; p-buried layer (PB); silicon-on-insulator (SOI); turn-OFF loss; turn-OFF loss.;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2015.2476469

Filename

7273900