Ultralow Turn-OFF Loss SOI LIGBT With p-Buried Layer During Inductive Load Switching

An ultralow turn-OFF loss (EOFF) silicon-oninsulator lateral insulated-gate bipolar transistor with a p-buried layer (PB SOT LTGBT) is first proposed. A universal EOFF model during inductive load turn-OFF is set up, which reveals that low EOFF can be achieved by reducing the total integral current charges, reducing the average anode voltage in the first phase and increasing the charge factor k. Due to the large capacitance effect and extra hole extraction path induced by the PB, the three ideas for low EOFF are demonstrated in the PB SOT LTGBT. Simulation results show that the PB SOT LTGBT can achieve an 85% lower EOFF compared with the conventional SOT LTGBT based on 6-μm SOT layer. Furthermore, the proposed EOFF model can be applied to all the TGBTs, and it reveals the mechanism of low EOFF of the TGBT with a superjunction structure during inductive load switching.