140 Gb/s Serializer Using Clock Doublers in 90 nm SiGe Technology

Many design challenges exist in achieving high frequency clocking for high-speed applications. This paper describes a new clock distribution technique and clocking approach with the use of clock doublers in close proximity to sub-circuits to achieve higher data rates, and in many cases, reduce design complexity and power in serializers. A half-rate 4:1 serializer using this unique frequency doubling clock distribution technique has been implemented in a 90 nm BiCMOS process. The design includes a 2¹⁰-1 pattern length LFSR with phase shifting logic as the testing circuit and a high bandwidth cascoded output driver. The chip has the dimensions of 1.8 × 2.2 mm ² and consumes 5.78 W from a -3.4 V supply voltage at 140 Gb/s.