Circuits for a Perpendicular Magnetic Anisotropic (PMA) Racetrack Memory

This paper deals with a so-called racetrack memory (also commonly known as a domain-wall memory). Novel circuits for implementing the write, the read, and the shift operations of a Perpendicular Magnetic Anisotropic (PMA) based racetrack cell are initially introduced; the proposed circuits are very efficient in terms of numerous figures of merit, such as delay, power dissipation, and power delay product (PDP). These circuits also allow an efficient implementation of array-level operations of a racetrack memory. An extensive simulation-based analysis is also presented; features such as variations and SEU tolerance in the operation of a PMA-based racetrack memory are considered. This analysis shows that a racetrack memory has great potential due to the significant advantages that it offers for non-volatile storage.