3613637

Bit-matrix decomposition and dynamic reconfiguration: a unified arithmetic processor architecture, d

Rong Lin

2002

6/24/1905 12:00:00 AM

"Testing","Computer architecture","Digital arithmetic","Graphics","Rendering (computer graphics)","Circuit simulation","Delay","Very large scale integration","Concurrent computing","Matrix decomposition"

ieee

Parallel and Distributed Processing Symposium., Proceedings International, IPDPS 2002, Abstracts and CD-ROM

0-7695-1573-8

conf

10.1109/IPDPS.2002.1016548

1016548