Title :
Minimizing the number of test configurations for FPGAs
Author_Institution :
Center for Reliable Comput., Stanford Univ., Palo Alto, CA, USA
fDate :
6/26/1905 12:00:00 AM
Abstract :
FPGA test cost can be greatly reduced by minimizing the number of test configurations. A test technique is presented for FPGAs with multiplexer-based routing architectures in which multiple logical paths through each multiplexer is enabled instead of only one path. It is shown that for Xilinx Virtex-II and Spartan-3 FPGAs only 8 test configurations are required to achieve 100% stuck-at, PIP stuck-on, and PIP stuck-off fault coverage.
Keywords :
"Field programmable gate arrays","Switches","Multiplexing","Routing","Logic testing","Circuit testing","Circuit faults","Costs","Logic design","Logic devices"
Conference_Titel :
Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on
Print_ISBN :
0-7803-8702-3
DOI :
10.1109/ICCAD.2004.1382702
