DocumentCode
3619488
Title
Selectively Grown Vertical Si p-MOS Transistor with Reduced Overlap Capacitances
Author
D. Klaes;J. Moers;A. Tonnemann;S. Wickenhauser;L. Vescan;M. Marso;P. Kordos;H. Luth;T. Grabolla
Author_Institution
Forschungszentrum J¨
fYear
1998
fDate
6/20/1905 12:00:00 AM
Firstpage
568
Lastpage
571
Keywords
"MOSFETs","Etching","Lithography","Epitaxial growth","High speed optical techniques","CMOS technology","Silicon","Parasitic capacitance","Packaging","Anisotropic magnetoresistance"
Publisher
ieee
Conference_Titel
Solid-State Device Research Conference, 1998. Proceeding of the 28th European
Print_ISBN
2-86332-234-6
Type
conf
DOI
10.1016/S0040-6090(98)01248-6
Filename
1503615
Link To Document