A Compact Implementation of Parasitic Inductance Cancellation for Shunt Capacitor Filters on Multilayer PCBs

Parasitic inductance limits the high-frequency performance of surface mount capacitors in a shunt filtering configuration. This paper introduces a new compact design for cancelling this parasitic inductance that makes use of magnetic coupling between vias, as well as between coplanar traces. This design is intended for use on PCBs with more than two layers, and is an extension of the designs presented in the recent paper by the authors, “Parasitic Inductance Cancellation for Surface Mount Shunt Capacitor Filters.” Implementations of the new design are shown to exhibit similar filtering performance to comparable implementations of previously published designs, while requiring nearly 40% less board area. Additionally, implementations of the design are demonstrated to be effective in the practical situation of filtering the noise due to crosstalk on a four-layer board.