Title :
LNA design for on-chip RF test
Author :
R. Ramzan;L. Zou;J. Dabrowski
Author_Institution :
Dept. of Electr. Eng., Linkoping Univ., Sweden
fDate :
6/28/1905 12:00:00 AM
Abstract :
In this paper we present two CMOS LNA blocks designed for integration with other RF frontend blocks for on-chip test. Both of them are variants of the source degenerated LNA with embedded switches and/or a multiplexer, optimized with respect to their function and location. We discuss their functionality and performances in terms of test mode and the normal operation mode. The circuits are designed for 0.35mum CMOS process. Simulation results obtained at 2.4 GHz frequency, show a tradeoff between performance and testability. Nevertheless, the LNA circuit, which only uses embedded switches, proves a satisfactory design
Keywords :
"Radio frequency","Circuit testing","Transceivers","Automatic testing","Bit error rate","Circuit faults","Fault detection","Crosstalk","Radiofrequency integrated circuits","Integrated circuit testing"
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1693564
