Title :
Mapping division algorithms to field programmable gate arrays
Author :
M.E. Louie;M.D. Ercegovac
Author_Institution :
Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
fDate :
6/14/1905 12:00:00 AM
Abstract :
The mapping of a fundamental arithmetic operation, division, to the Xilinx XC4010, a lookup-table based FPGA (field-programmable gate array) is examined. It is shown how steps within the division algorithm can be merged by utilizing FPGAs and how parallelism can be exploited for optimal-performance FPGA implementations. Some mapping tradeoffs to reduce either the delay or the required number of logic blocks are shown.
Keywords :
"Field programmable gate arrays","Arithmetic","Delay estimation","Hardware","Logic","Throughput","Timing","Routing","Computer science","Silicon"
Conference_Titel :
Signals, Systems and Computers, 1992. 1992 Conference Record of The Twenty-Sixth Asilomar Conference on
Print_ISBN :
0-8186-3160-0
DOI :
10.1109/ACSSC.1992.269172
