• DocumentCode
    3625303
  • Title

    A 1GHz Direct Digital Frequency Synthesizer Based on the Quasi-Linear Interpolation Method

  • Author

    Ashkan Ashrafi;Aleksandar Milenkovic;Reza Adhami

  • Author_Institution
    Department of Electrical and Computer Engineering, The University of Alabama in Huntsville, Huntsville, AL 35899, USA
  • fYear
    2007
  • fDate
    5/1/2007 12:00:00 AM
  • Firstpage
    2766
  • Lastpage
    2769
  • Abstract
    The paper presents a novel architecture for a direct digital frequency synthesizer (DDFS) based on the quasi-linear interpolation (QLIP) method. The four-segment QLIP is utilized to realize a DDFS with a spurious free dynamic range (SFDR) of 63.2dBc. The DDFS chip featuring a 5-stage pipeline is implemented in TSMC 0.13mum technology. The chip occupies 9874mum2 , consumes 8.2muW/MHz, and runs at 1GHz clock rate.
  • Keywords
    "Frequency synthesizers","Interpolation","Polynomials","Clocks","Upper bound","Dynamic range","Energy consumption","Signal generators","Spread spectrum radar","Spread spectrum communication"
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
  • ISSN
    0271-4302
  • Print_ISBN
    1-4244-0920-9
  • Electronic_ISBN
    2158-1525
  • Type

    conf

  • DOI
    10.1109/ISCAS.2007.378626
  • Filename
    4253251
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3625303