• DocumentCode
    3628050
  • Title

    A dual-core programmable decoder for LDPC convolutional codes

  • Author

    Marcos B.S. Tavares;Emil Matus;Steffen Kunze;Gerhard P. Fettweis

  • Author_Institution
    Technische Universit?t Dresden, D-01062, Germany
  • fYear
    2008
  • fDate
    5/1/2008 12:00:00 AM
  • Firstpage
    532
  • Lastpage
    535
  • Abstract
    We present the concepts and realization of a highly parallelized decoder architecture for LDPC convolutional codes and tail-biting LDPC convolutional codes. This architecture has a very good scalability and is fully programmable so that it can be applied to several communications and data storage scenarios. The synthesis results show relatively small area consumption for very high decoding speeds.
  • Keywords
    "Decoding","Parity check codes","Convolutional codes","Computer architecture","Throughput","Interleaved codes","Memory architecture","Scalability","Tail","Equations"
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
  • ISSN
    0271-4302
  • Print_ISBN
    978-1-4244-1683-7
  • Electronic_ISBN
    2158-1525
  • Type

    conf

  • DOI
    10.1109/ISCAS.2008.4541472
  • Filename
    4541472
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3628050