FPGA design of arbitrary down-sampler

This paper describes the FPGA design of an arbitrary down-sampler. The arbitrary down-sampler performs decimation of the input signal, adjusting its sample rate to the requirements on the system output. The solution presented in this paper introduces the down-sampler that can adjust its resampling ratio to whatever output frequency if it is in the range within estimation provided. Resource utilization for an FPGA implementation on Xilinx Virtex4 chip is also summarized.