Overestimation of Short-Channel Effects Due to Intergate Coupling in Advanced FD-SOI MOSFETs

Author

Navarro, C. ; Bawedin, M. ; Andrieu, F. ; Cristoloveanu, S.

Author_Institution

Inst. d´Electron. du Sud, Univ. of Montpellier II, Montpellier, France

Volume

61

Issue

9

fYear

2014

fDate

Sept. 2014

Firstpage

3274

Lastpage

3281

Abstract

The short-channel effects (SCE) in advanced fully depleted silicon-on-insulator MOSFETs are investigated by showing the importance of the intergate coupling. Experimental results highlight that part of the SCE is due to the contribution of the opposite-gate, leading to systematic overestimation of the threshold voltage roll-off and drain-induced barrier lowering (DIBL) effects. Numerical simulations confirm that the impact of back-gate SCE depends on the device structure (film and oxide thickness) and bias. A basic model is presented, which enables the identification of the genuine SCE at each gate. To mitigate or fully cancel the threshold voltage roll-off and DIBL, we propose simple and pragmatic back-biasing schemes.

Keywords

MOSFET; numerical analysis; semiconductor device models; silicon-on-insulator; DIBL effects; advanced FD-SOI MOSFETs; back-gate SCE; coupling integration; device structure; drain-induced barrier lowering effects; fully depleted silicon-on-insulator; genuine SCE identification; numerical simulations; pragmatic back-biasing schemes; short-channel effect overestimation; threshold voltage roll-off systematic overestimation; Couplings; Logic gates; MOSFET; Silicon; Threshold voltage; Voltage measurement; Back-biasing; DIBL; FD SOI; MOSFET; SOI; inter-gate coupling; overestimation; roll-off; short-channel effects;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2014.2338081

Filename

6880446