DocumentCode :
3632799
Title :
FPGA implementation of an acoustic echo canceller using a VSS-NLMS algorithm
Author :
Cristian Anghel;Constantin Paleologu;Jacob Benesty;Silviu Ciochina
Author_Institution :
Department of Telecommunications, University Politehnica of Bucharest, Romania
fYear :
2009
Firstpage :
1
Lastpage :
4
Abstract :
Many interesting adaptive algorithms have been proposed for acoustic echo cancellation. Even if they exhibit good performance in “infinite” precision, their capabilities could be seriously affected when using practical implementation platforms, e.g., digital signal processor (DSP) or field-programmable gate array (FPGA). In this context, several finite-precision effects could seriously bias the acoustic echo canceller (AEC) behavior. In this paper, we present an FPGA implementation of an AEC based on a recently proposed variable step-size normalized least-mean-square (VSS-NLMS) algorithm. Area and speed results are provided for a XC2S600E chip. The overall performance of this AEC indicates that it could be a reliable solution for real-world acoustic echo cancellation scenarios.
Keywords :
"Field programmable gate arrays","Echo cancellers","Signal processing algorithms","Acoustic devices","Adaptive filters","Adaptive algorithm","Digital signal processors","Digital signal processing","Microphones","Computational complexity"
Publisher :
ieee
Conference_Titel :
Signals, Circuits and Systems, 2009. ISSCS 2009. International Symposium on
Print_ISBN :
978-1-4244-3785-6
Type :
conf
DOI :
10.1109/ISSCS.2009.5206121
Filename :
5206121
Link To Document :
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