FPGA-accelerated retinal vessel-tree extraction

This work introduces an FPGA implementation for vesseltree extraction on retinal images. The retinal vessel-tree can be used in disease diagnoses, e.g. diabetes, or in person authentication. In such cases, a portable device with a high performance may be a need. The FPGA implementation discussed here, although application-oriented, features a fully programmable SIMD architecture, allowing for an efficient realization of low-level image processing algorithms. It is mapped onto a Spartan 3, amounting to 90 processing elements. The on-chip memory utilized was 1.4MB and stores 8 gray images of 144 × 160px. The working frequency is 53MHz, allowing for a 3 × 3 convolution in less than 110μs.