DocumentCode
3633539
Title
DC characteristics of Junction Vertical Slit Field-Effect Transistor (JVeSFET)
Author
Andrzej Pfitzner;Michal Staniewski;Michal Strzyga
Author_Institution
Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Poland
fYear
2009
Firstpage
420
Lastpage
423
Abstract
This paper presents a simulation based feasibility study of deep-submicron JFETs obeying an extreme layout regularity, that is a foundation of a new Vertical Slit geometry ICs (VeSTICs) vision proposed in [4]. DC characteristics obtained for symmetrical dual gate JVeSFETs have been investigated in a wide range of bias voltages. As a conclusion an assessment of applicability of these devices in nano-size era SoCs is proposed.
Keywords
"FETs","JFETs","Geometry","Solid modeling","Silicon on insulator technology","Electrodes","Threshold voltage","Integrated circuit layout","Microelectronics","Integrated circuit technology"
Publisher
ieee
Conference_Titel
Mixed Design of Integrated Circuits & Systems, 2009. MIXDES ´09. MIXDES-16th International Conference
Print_ISBN
978-1-4244-4798-5
Type
conf
Filename
5289571
Link To Document