Design of pixel readout integrated circuits in submicron technology to minimize the mismatch effects

Modern pixel detectors working in single photon counting mode require fast, high density readout electronics. The large readout ASIC for these detectors consists of several thousands of readout pixels, while the area of a single pixel containing both analog and digital blocks is often less than 100×100 µm² with the power consumption limited to a few tens of μW. To ensure the full functionality of a single readout pixel (amplification, filtering and data storage) VLSI designers more often use submicron CMOS technologies (0.25 µm – 90 nm). However, strict power and area limitations for the readout electronics cause that one of the most demanding factors during the design process is the uniformity of analog parameters for large pixel matrix. The transistors in analog blocks often work in weak or moderate inversion where effects of variability of the transistor parameters become more visible. Additionally, in large pixel matrix containing several thousands of pixel cell units (PCU) one has to take into account possible voltage drops on power supply and reference lines. The above effects can be reduced by the careful design of the PCU itself with a strict power limitation, proper power supply and reference distribution together with adding an offset correction circuit working in each channel independently.