Title :
A 2.89mW 50GOPS 16×16 16-core MIMO sphere decoder in 90nm CMOS
Author :
Chia-Hsiang Yang;Dejan Markovic
Author_Institution :
University of California, Los Angeles, USA
Abstract :
A 16-core multi-input multi-output (MIMO) decoder for agile communication systems is implemented in a low-VT 90nm CMOS technology. This chip implements the sphere decoding algorithm and is highly flexible to support multiple configurations: antenna arrays from 2×2 to 16×16, modulations from BPSK to 64QAM, and up to 128 data streams. Operating at 16MHz, the chip provides 50GOPS (12-bit add equivalent) in the 16×16, 64QAM mode. It consumes 2.89mW of power with a 321mV supply voltage, resulting in a power efficiency of 17.3GOPS/mW. At 256MHz, the peak data rate exceeds 1.5Gbps over a 16MHz channel.
Keywords :
"MIMO","Maximum likelihood decoding","Computer architecture","CMOS technology","Maximum likelihood estimation","Receiving antennas","Antenna arrays","Telecommunication network reliability","Computational complexity","Hardware"
Conference_Titel :
ESSCIRC, 2009. ESSCIRC ´09. Proceedings of
Print_ISBN :
978-1-4244-4355-0;978-1-4244-4354-3
DOI :
10.1109/ESSCIRC.2009.5325957
