Log-domain CMOS implementation of a class of analog parallel architectures

Log-domain CMOS implementation of a class of linear continuous in time and discrete in space homogeneous cellular neural network type analog parallel architectures are discussed. The specific feature of the spatio-temporal dynamics of the array is that it exhibits unstable spatial modes - property which can be used for high speed image processing. The dynamics and spatial frequency response of a 1D array at system level and log-domain transistor level implementation are compared.