Title :
On reducing transition counts in sign detection circuits
Author :
M.D. Ercegovac;C. Fabian;T. Lang
Author_Institution :
Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Abstract :
An approach to reducing the average number of signal transitions in the networks for sign-detection and comparison of magnitudes is evaluated at the gate level. We implemented the circuit in 0.6 micron CMOS technology, and performed simulations to substantiate the claims of reducing total power consumption, with little penalty on speed or size. The simulation verifies that the approach significantly reduces the average number of transitions.
Keywords :
"Iterative algorithms","CMOS technology","Capacitance","Intelligent networks","Computer networks","Computational modeling","Circuit simulation","Energy consumption","Digital integrated circuits","Capacitors"
Conference_Titel :
Signals, Systems and Computers, 1995. 1995 Conference Record of the Twenty-Ninth Asilomar Conference on
Print_ISBN :
0-8186-7370-2
DOI :
10.1109/ACSSC.1995.540617
