Methodology for simulated power analysis attacks on AES

This paper presents detailed methodology for performing simulated Power Analysis Attacks (PAAs) on gate level models of cryptographic components with Synopsys design tools. First the Advanced Encryption Standard (AES) hardware model is developed for the experiment using VHDL. The model is then synthesized with Synopsys DesignCompiler and the 130-nm CMOS standard cell library. Simulated instantaneous power consumption waveforms are generated with Synopsys PrimeTime PX. Results are analyzed and successful single and multiple-bit Differential Power Analysis (DPA) attacks are performed on the waveforms. The AES hardware model did not implement any DPA countermeasure techniques.