Analog synchronous receiver for multi-gigabit wireless communications

In this work, we present a synchronous receiver architecture utilizing analog carrier recovery, to be used in multi-gigabit wireless communication systems. Carrier phase and frequency synchronization in the analog receiver drastically reduces cost and simplifies the system design by enabling the usage of 1-bit resolution analog to digital converters (ADC). The focus of this work is mainly the analog carrier recovery, which forms the basis of the proposed receiver. Simulation and experimental results are presented, demonstrating the applicability of the presented analog receiver concept for multi-gigabit communication links.