DocumentCode :
3641084
Title :
Test time reduction in analogue/mixed-signal devices by defect oriented testing: An industrial example
Author :
Hamidreza Hashempour;Jos Dohmen;Bratislav Tasić;Bram Kruseman;Camelia Hora;Maikel van Beurden;Yizi Xing
Author_Institution :
NXP Semiconductors, Central R&
fYear :
2011
fDate :
3/1/2011 12:00:00 AM
Firstpage :
1
Lastpage :
6
Abstract :
We present an application of Defect Oriented Testing (DOT1) to an industrial mixed signal device to reduce test time and maintain quality. The device is an automotive IC product with stringent quality requirements and a mature test program that is already in volume production. A complete flow is presented including defect extraction, defect simulation, test selection, and validation. A major challenge of DOT for mixed signal devices is the simulation time. We address this challenge with a new fault simulation algorithm that provides significant speedup in the DOT process. Based on the fault simulations, we determine a minimal set of tests which detects all defects. The proposed minimal test set is compared with the actual test results of more than a million ICs. We prove that the production tests of the device can be reduced by at least 35%.
Keywords :
"Circuit faults","Integrated circuit modeling","Production","US Department of Transportation","Bridge circuits","Testing","Analytical models"
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011
ISSN :
1530-1591
Print_ISBN :
978-1-61284-208-0
Type :
conf
DOI :
10.1109/DATE.2011.5763065
Filename :
5763065
Link To Document :
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