QDEC machine increased reliability in programmable FPGA circuit

The article deals with the design, simulation and implementation of QDEC (Quadrature Decoder) machine with increased reliability (QDEC2) for implementation in a programmable FPGA (Field Programmable Gate Array) circuit. The purpose of research activities of reliable QDEC2 in the FPGA is the incorporation of this model to control of the robot. In the first part of the article describes the possibility of machine. In the second part are describe the state machine diagram and the algebraic description of the behavior. In the third section of article are provides the selected results from the simulation of error-free and fault states machine.