DocumentCode :
3645575
Title :
Analysis of impact of FPGA routing architecture parameters on area and delay
Author :
Christopher Schäfer;Mirjana Stojilović;Lazar Saranovac
Author_Institution :
Technical University Munich, Arcisstrasse 21, Munich, Germany
fYear :
2011
Firstpage :
924
Lastpage :
927
Abstract :
FPGAs are increasingly replacing more expensive microprocessors and ASICs in a wide variety of applications. Their performance is limited mainly by the characteristics of the routing network. This paper presents a detailed study of the influence of the parameters defining an FPGA routing network on the routing area, the critical path delay, and the channel width required to place and route benchmark circuits. The goal was to find the set of parameter values providing maximal performance of the routing network. The results have shown that the trade-offs are inevitable.
Keywords :
"Routing","Field programmable gate arrays","Delay","Benchmark testing","Design automation","Switches","USA Councils"
Publisher :
ieee
Conference_Titel :
Telecommunications Forum (TELFOR), 2011 19th
Print_ISBN :
978-1-4577-1499-3
Type :
conf
DOI :
10.1109/TELFOR.2011.6143696
Filename :
6143696
Link To Document :
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