Cost estimation of nanoscale partial defect tolerant arrays

High defect rates are common in nanotechnology and fabrication has to deal with increasing variations and percent of mortality rates. Qualitative changes are introduced in circuit design to make nanoscale architectures less prone to defects. Fault tolerant techniques will be crucial to the use of nano-electronics in the future. On architectural level, partial defect tolerant design can be a candidate method to decrease overall fabrication costs. The goal of this paper is to estimate costs of nanotechnology fabrications of partial defect tolerant systolic arrays with different topologies. With aim to investigate the possibilities for nanoscaling of partial defect tolerant arrays with different topologies the yield analysis procedure will be given. We will consider 1D systolic array for matrix-vector multiplication and 2D bit-plane semi-systolic array. Fabrication cost savings for partial defect tolerant nanoscale designs will be analytically obtained and illustrated on FPGA implementation of the arrays.