Fault tolerant pseudorandom number generator

Performance and fault tolerance, FT, are two dominant issues during development of complex real-time embedded systems, RT_ES. FT is generally accomplished by using redundancy in hardware, software, time, or combination thereof. Triple modular redundancy, TMR, is one of the most popular FT hardware scheme which uses spatial redundancy. In this paper a design of FT psedorandom generator, FT_PRNG, based on TMR voting principle, is described. The design of FT_PRNG is of practical interest in testing complex CMOS VLSI ICs in the presence of single event upsets (SEUs), especially in a case when the design is SRAM based. The FT_PRNG was implemented on FPGA technology. Finally, the performance of the FT_PRNG in respect to speed of operation, hardware overhead and power consumption are estimated.