DocumentCode :
3652200
Title :
Adder circuits using symmetric and asymmetric FinFETs
Author :
Farid Moshgelani;Dhamin Al-Khalili;Come Rozon
Author_Institution :
Dept. of Electr. &
fYear :
2013
Firstpage :
23
Lastpage :
26
Abstract :
In this paper we are examining different configurations and circuit topologies for adder circuits using both symmetric and asymmetric work-function FinFET transistors. Based on extensive characterization data, for the carry generation of a mirror full adder using symmetric devices, both leakage current and delay are decreased by 25% and 50% respectively compared to results in the literature. For the 14 transistor (14T) full adder topology, both leakage and delay are decreased by 23% and 29% respectively compared to the mirror topology. The 14T adder topology, using asymmetric devices without any additional power supply, achieves reduction in leakage by 85% with a small degradation of 7% in delay. All simulations are based on 25nm FinFET technology using the University of Florida UFDG model.
Keywords :
"Adders","FinFETs","Logic gates","Leakage currents","Topology","Mirrors"
Publisher :
ieee
Conference_Titel :
Instrumentation and Measurement, Sensor Network and Automation (IMSNA), 2013 2nd International Symposium on
Type :
conf
DOI :
10.1109/IMSNA.2013.6742809
Filename :
6742809
Link To Document :
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