• DocumentCode
    3659149
  • Title

    Gate-stack engineering for self-aligned Ge-gate/SiO2/SiGe-channel Insta-MOS devices

  • Author

    Wei-Ting Lai;Kuo-Ching Yang;Po-Hsiang Liao;Thomas George;Pei-Wen Li

  • Author_Institution
    National ChiaoTung University, HsinChu, Taiwan, 300, Republic of China
  • fYear
    2015
  • fDate
    6/1/2015 12:00:00 AM
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    We reported a first-of-its-kind, self-aligned gate-stack heterostructure of Ge-nanoshpere-gate/SiO2/SiGe-channel on Si in a single-step approach through selective oxidation of a SiGe nano-patterned pillar over a Si3N4 buffer layer on Si substrate. Good tunability on the Ge-nanoshpere size, SiO2 thickness, and SiGe-shell thickness provides a practically-achievable core building block for Ge-based metal-oxide-semiconductor (MOS) devices with size-tunable Ge gates, SiO2 gate oxide, and SiGe channels. Detailed interfacial morphologies and structural properties between the Ge nanosphere/SiO2 and SiO2/SiGe-channel were examined using transmission electron microscopy, energy dispersive x-ray spectroscopy, and temperature-dependent high/low-frequency capacitance-voltage measurements. Both Al/SiO2/Ge-nanospheres and NiGe/SiO2/SiGe MOS capacitors exhibit quite low interface trap densities of 3-5×1011 cm-2eV1, which is beneficial for advanced Ge MOS applications.
  • Keywords
    "Logic gates","Silicon","Silicon germanium","Oxidation","Substrates","Capacitors","Capacitance-voltage characteristics"
  • Publisher
    ieee
  • Conference_Titel
    Silicon Nanoelectronics Workshop (SNW), 2015
  • Type

    conf

  • Filename
    7275283