Title :
A capacitance-voltage model for DG-TFET
Author :
Arnab Biswas;Adrian M. Ionescu
Author_Institution :
Ecole Polytechnique Fé
fDate :
6/1/2015 12:00:00 AM
Abstract :
In this work we develop a simplified capacitance model for Double Gate TFETs. Capacitance-voltage measurements were done on all-Silicon SOI TFETs at different biasing schemes to support the model development. TCAD simulations [1] of DG-TFETs were used to validate the model.
Keywords :
"Logic gates","Capacitance","Computational modeling","Capacitance measurement","Biological system modeling","Voltage measurement","Current measurement"
Conference_Titel :
Silicon Nanoelectronics Workshop (SNW), 2015
