VLSI implementation of bit serial architecture based multiplier in floating point arithmetic

VLSI implementation of Neural network processing or digital signal processing based applications comprises large number of multiplication operations. A key design issue, therefore in such applications depends on efficient realization of multiplier block which involves trade-off between precision, dynamic range, area, speed and power consumption of the circuit. The study in this paper investigates performance of VLSI implementation of bit serial architecture based multiplier (Type III) in floating point arithmetic (IEEE 754 Single Precision format). Results of implementation of 32x32 bit multiplier on FPGA as well as on Backend VLSI Design tool indicate that bit serial architecture based multiplier design provides good trade-off in terms of area, speed, power and precision over array multiplier and other multipliers approach proposed since last decade. In other words, bit serial architecture based multiplier (Type III) approach may provide good multi-objective solution for VLSI circuits.