Title :
Product Level MTBF Calculation
Abstract :
Synchronizers are used in sampling an asynchronous data for digital circuits. It protects the chips from metastability failure. As mean time between failure degrade with technology scaling while chip performance increase with multiple clock domain on chip and the synchronizer chain´s usage increase, the mean time between failure, MTBF requirements is getting tougher to meet with technology scaling. The objective of this paper is to share the proper N number of synchronizer chains calculation as well as the product level mean time between failure, MTBF´s derivation and the caveats of using traditional product level´s mean time between failure, MTBF estimation. Hopefully the sharing will benefit the readers.
Keywords :
"Synchronization","Mathematical model","Clocks","Flip-flops","Delays","Latches","Integrated circuit modeling"
Conference_Titel :
Intelligent Systems, Modelling and Simulation (ISMS), 2014 5th International Conference on
DOI :
10.1109/ISMS.2014.137