Title :
Value analysis for the determination of memory instruction latency in a WCET tool
Author :
Karila Palma Silva;Renan Augusto Starke;Rômulo Silva de Oliveira
Author_Institution :
Department of Systems Automation, Fed. Univ. Santa Catarina (UFSC), Florianó
fDate :
7/1/2015 12:00:00 AM
Abstract :
This paper presents a method to determine the latency of memory instructions, aimed for use in WCET tools. We use a technique known as value analysis. Considering a processor with different data memory latencies, value analysis is used to determine the possible values of processor registers statically, allowing the recognition of memory addresses (main memory or ScratchPad Memory) in order to obtain tighter WCET upper bounds.
Keywords :
"Registers","Random access memory","Analytical models","Timing","Real-time systems","Process control","Pipelines"
Conference_Titel :
Industrial Informatics (INDIN), 2015 IEEE 13th International Conference on
Electronic_ISBN :
2378-363X
DOI :
10.1109/INDIN.2015.7281743
