DocumentCode :
3662574
Title :
An input pole tuned switching equalization scheme for high-speed serial links
Author :
Sanquan Song; Jian Xu; Fengxiang Cai; Xin Ma; Zibing Yang;Matthew Becker;Larry Tate; Byungsub Kim;Samuel Palermo;Bill Bowhill
Author_Institution :
Samsung Display American Lab, 217 Devcon Drive, San Jose CA, USA
fYear :
2015
Firstpage :
1
Lastpage :
4
Abstract :
A novel receiver equalization scheme for high-speed links is described in this paper. By per-bit switching the channel-receiver connection, the channel induced inter-symbol interference (ISI) is compensated by receiver (RX) input pole induced ISI. The polarity of the recovered binary bit is adjusted in digital domain to match the transmitted data. An input pole based two-way interleaved switching equalization circuit is proposed and simulated. In comparison with the conventional FIR filter, it improves the output eye width by 63%. This paper provides a new way of converting a low-pass system into a peaking system for link designs, suitable for a broader range of applications.
Keywords :
"Switches","Filtering theory","Resistors","Clocks","Attenuation","CMOS integrated circuits"
Publisher :
ieee
Conference_Titel :
Circuits and Systems (MWSCAS), 2015 IEEE 58th International Midwest Symposium on
Type :
conf
DOI :
10.1109/MWSCAS.2015.7282031
Filename :
7282031
Link To Document :
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