Title :
A 40Gb/s 39mW 3-tap adaptive closed-loop decision feedback equalizer in 65nm CMOS
Author :
Weidong Cao; Ziqiang Wang; Dongmei Li; Xuqiang Zheng; Fule Li; Chun Zhang; Zhihua Wang
Author_Institution :
Tsinghua National Laboratory for Information Science and Technology, Institute of Microelectronics, Tsinghua University, Beijing, China
Abstract :
This paper describes design techniques of enabling energy-efficient 3-tap decision feedback equalizer (DFE) to operate adaptively at 40Gb/s in 65nm CMOS technology. First, we propose a closed-loop architecture utilizing three techniques to achieve the 1st tap stage design, namely a merged latch and summer, reduced latch gain, and a dynamic latch design. Then, we suggest to merge the feedback MUX with the tap differential pairs within the clock-control summers array (CCSA) to accomplish the 2nd and 3rd tap stages design. Last, the sign-sign least-mean square (SSLMS) algorithm is adopted in the DFE to adjust the tap weight automatically. The total power consumption of the 3-tap DFE core is 39mW under 1V supply, achieving 1 pJ/bit energy efficiency.
Keywords :
"Latches","Decision feedback equalizers","Least squares approximations","Delays","Clocks","Power demand"
Conference_Titel :
Circuits and Systems (MWSCAS), 2015 IEEE 58th International Midwest Symposium on
DOI :
10.1109/MWSCAS.2015.7282043