A near-threshold SRAM design with transient negative bit-line voltage scheme

With the percentage of embedded SRAM increasing in SoC chip, low-power design such as near-threshold SRAM technique is getting more and more attention to reduce entire chip energy consumption. However, the descending operating voltage will lead to longer write latency and higher failure rate. In this work, we present near-threshold SRAM design in which transient negative bit-line is employed as periphery assisting techniques for the first time. Simulations show in 40nm technology the write ability manifest 15× speedup over the conventional case at 0.6V supply voltage and 1M-cell SRAM array design can work under near-threshold supply voltage with 90% yield.