Title :
Leakage reduction in stacked sub-10nm double-gate MOSFETs
Author :
Woo-Suhl Cho;Kaushik Roy
Author_Institution :
School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47906, USA
Abstract :
In this paper, the effectiveness of transistor stacking (or supply-gating) to reduce the leakage in the standby-mode of operation of sub-10nm double-gate MOSFETs is investigated. For that purpose, device parameters such as symmetric/asymmetric gate-to-source/drain underlap and body thickness are optimized to improve the ON-state current to the OFF-state current ratio. The optimized devices are then used in circuit simulation to analyze the dependence of each major leakage source (direct source-to-drain tunneling, thermionic, and gate oxide leakage currents) on the device geometry (tsi and symmetry in LUN) and input vectors for two- and three-stacked transistors. The analysis shows that supply-gating is effective in reducing direct source-to-drain current as well as thermionic leakage in the stand-by mode of operation for sub-10nm technology.
Keywords :
"Logic gates","Leakage currents","MOSFET","Tunneling","Integrated circuit modeling","Stacking"
Conference_Titel :
Simulation of Semiconductor Processes and Devices (SISPAD), 2015 International Conference on
Print_ISBN :
978-1-4673-7858-1
DOI :
10.1109/SISPAD.2015.7292331