DocumentCode :
3667985
Title :
Sandwiched-gate inverter: Novel device structure for future logic gates
Author :
Myunghwan Ryu;Franklin Bien;Youngmin Kim
Author_Institution :
School of Electrical and Computer Engineering, Ulsan National Institute of Science and Technology (UNIST), Republic of Korea
fYear :
2015
Firstpage :
442
Lastpage :
445
Abstract :
In this paper, we propose a novel sandwiched-gate inverter by using of an NMOS GAA together with a donut-type PMOS. The DC operation and the transient performance of the proposed inverter were investigated with 3D TCAD simulations. The proposed inverter exhibits a correct inverter operation with a high noise margin and speed.
Keywords :
"Inverters","Logic gates","MOS devices","Noise","Transistors","Silicon","Transient analysis"
Publisher :
ieee
Conference_Titel :
Simulation of Semiconductor Processes and Devices (SISPAD), 2015 International Conference on
ISSN :
1946-1569
Print_ISBN :
978-1-4673-7858-1
Type :
conf
DOI :
10.1109/SISPAD.2015.7292356
Filename :
7292356
Link To Document :
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